In this example we will perform the thermal stress analysis of a bi-metallic strip. We will build the entire model from geometric construction so that we can apply loads directly on the geometry. The dimension of the bi-metallic strip is one inch by one inch. The thickness for the solder type material is 0.05 inch, and the thickness of the Ge material is 0.025 inch. Thus the assembly thickness is 0.075 inch.

The top surface temperature boundary condition is -30 oC, and the bottom surface temperature boundary condition is 70 oC. We will determine the temperature distribution by running a steady-state thermal analysis.

Prior to the development of the Patran MD Nastran Heat Transfer interface, one would request:

TEMP(PUNCH)=all

in the MD Nastran Case Control section of the thermal run. The temperature load is then created and saved inside the punch file. In the subsequent thermal stress analysis one can access this file by defining

TEMP(LOAD)=1

in the Case Control section of the ensuing stress analysis run.

However, using Patran you can use the Create-Spatial-FEM command after you have postprocessed the thermal result in the viewport. We will use this technique to apply a thermal load for the stress analysis. Also, we will analyze the thermal stress analysis for the free-free expansion by enforcing a minimum number of constraints to fix-rigid body motion.

 

The reference or zero stress state for the assembly is initialized at -30 oC. The thermal coefficient of expansion for the solder is approximately four times that of Ge. When the temperature gradient associated with the temperature boundary conditions is applied, the solder layer wants to grow significantly more than the Ge layer due not only to the higher coefficient of thermal expansion, but also because of the higher temperature relative to TREF. The Ge layer ends up with a more complex stress pattern due to its four corner points being constrained, the distribution of temperature through the layer, and the growth enforced by the solder layer. The free surface of the solder layer exhibits the low stress levels.